1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method for use in an integrated circuit, and more particularly to a semiconductor device manufacturing method for manufacturing a high-speed, low power consumption CMOS logic circuit element, an analog RF circuit element or the like including a strained Si and SiGe channel MOSFET.
2. Description of the Related Art
In recent years, the technical and economic barriers have become great to shorten a gate length of a field effect transistor (MOSFET). To relax this situation, a technology which uses a high-mobility channel material, especially strained Si (or strained SiGe) has attracted attention. Since the strained Si is formed on a lattice-relaxed SiGe wit a larger lattice constant, mobilities of both of electrons and holes increase by in-plane tensile strain. The strain amount of the strained Si becomes large as a Ge composition in a substrate SiGe becomes large, and hence the mobility becomes higher. If a CMOS includes a MOSFET having the strained Si channel, an operation higher than a Si-CMOS with the same size can be expected.
The present inventors have presented a MOSFET (strained SOI-MOSFET) in which the strained Si is combined with an Si-On-Insulator (SOI) structure, and substantiated its operation (T. Mizuno, S. Takagi, N. Sugiyama, J. Koga, T. Tezuka, K. Usuda, T. Hatakeyama, A. Kurobe, and A. Toriumi, IEDM Technical Digest, p. 934 (1999)).
This element is formed by sequentially stacking an buried oxide film, a lattice-relaxed SiGe buffer layer, a strained Si channel, a gate oxide film and a gate electrode film on a Si substrate. This structure has some advantages due to high carrier mobility of the strained Si, and a merit due to the SOI structure, such as a capability of reducing junction capacitance and a capability of downsize while maintaining a low impurity concentration. Therefore, if a CMOS logic circuit includes this structure, a higher speed and lower power consumption operation becomes possible.
In order to put the aforementioned element to practical use, a nearly completely lattice-relaxed Si1-xGex buffer layer of a low dislocation density is necessary. Usually, the lattice constant of the SiGe thin film, which is grown with epitaxial growth on the Si substrate, parallel to the substrate coincides with that of the Si and only the lattice constant thereof vertical to the substrate is larger than that of the Si. That is, the SiGe thin film is strained SiGe layer having the compressive strain in the substrate surface. Even if the Si is grown with epitaxial growth on the compressively strained SiGe layer, the strain is not introduced into the Si layer. Therefore, to obtain the SiGe buffer layer for growing strained Si layer with epitaxial growth, it is necessary to lattice-relax the strained SiGe layer by some means. As a method for obtaining such a buffer layer, the present inventors have presented a method which thermally oxidizes an SiGe layer of a low Ge composition (x=0.1) formed on an oxide film at a high temperature to simultaneously achieve lattice relax and film thinning while increasing the Ge composition (x>0.5) (oxidation condensation) (Jpn. Pat. Appln. KOKAI Publication No. 2002-76347). An SiGe thin film grown with epitaxial growth on the SOI can also be subjected to oxidation condensation (T. Tezuka et al, Appl. Phys. Lett. 79, p 1798 (2001)).
In order to obtain high mobility by sufficiently straining the Si channel layer, the substrate SiGe layer must be sufficiently lattice-relaxed. On the other hand, in order to obtain reliability and reduce a leakage current, occurrence of lattice defects such as dislocation must be suppressed. However, in the conventional oxidation condensation, there has been a difficulty of lowering a threading dislocation density to a value of about 103 cm−2, which becomes a practical target, while sufficiently relaxing a lattice.
On the other hand, to promote the relaxation of the SiGe layer on the SOI, a method, which implants B (boron) ions into the buried oxide film and is annealed, has been presented (F. Y. Huang et al., Appl. Phys. Lett. Vol. 19, pp. 2680–2682 (2000)). According to this method, since the mixing of B in the oxide film greatly lowers a softening temperature of the oxide film, there is a possibility of obtaining a high relaxation rate even at an annealing temperature of about 800° C. without introducing dislocation. However, because of its very large diffusion coefficient at the oxidation temperature, B is easily diffused in the Si layer or the SiGe layer on the oxide film during the annealing process. B becomes p type impurities for Si. Thus, all the semiconductor layers on an insulating film are doped to be p types with high concentrations, which make manufacturing of a CMOS extremely difficult.
As described above, to put the strain SOI-MOSFET to practical use, the sufficiently lattice-relaxed SiGe buffer layer with the low dislocation density is required. However, it is difficult to form the lattice-relaxed SiGe thin film on the insulating film without introducing dislocation and impurity diffusion.